发明名称 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKED DIE
摘要 An integrated circuit package system with an offset stacked die is provided to implement straightforward, cost-effective, uncomplicated, accurate, sensitive, effective processes and constructions. An integrated circuit package system with an offset stacked die includes: providing a first integrated circuit die(110); adhering a second integrated circuit die(112) over the first integrated circuit die and offsetting from the first integrated circuit die in one dimension; forming an inter-die layer(102) over the second integrated circuit die; adhering a third integrated circuit die(114) over the inter-die layer and substantially aligning them to the second integrated circuit die; and adhering a fourth integrated circuit die(116) over the third integrated circuit die and offsetting from the third integrated circuit die in the same amount and substantially an opposite direction as the second integrated circuit die to the first integrated circuit die.
申请公布号 KR20080058186(A) 申请公布日期 2008.06.25
申请号 KR20070129217 申请日期 2007.12.12
申请人 STATS CHIPPAC LTD. 发明人 CHIN CHEE KEONG
分类号 H01L23/12 主分类号 H01L23/12
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