发明名称 Centralized memory based packet switching system and method
摘要 A packet switching system and method are disclosed. The system includes a plurality of input and output ports and an input buffer at each of the input ports. The system further includes an input scheduler associated with each of the input buffers and a centralized memory shared by the output ports. An output buffer is located at each of the output ports and an output scheduler is associated with each of the output ports. Each of the input buffers comprises a plurality of virtual output queues configured to store a plurality of packets in a packed arrangement.
申请公布号 US7391786(B1) 申请公布日期 2008.06.24
申请号 US20020305639 申请日期 2002.11.27
申请人 CISCO TECHNOLOGY, INC. 发明人 PRASAD SHARAT;SEAVER TERRY;WANG YANFENG;DENG YU;HERNANDEZ LUIS M.
分类号 H04L12/28;H04L12/54 主分类号 H04L12/28
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