发明名称 |
Multi-threshold CMOS latch circuit |
摘要 |
Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.
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申请公布号 |
US7391249(B2) |
申请公布日期 |
2008.06.24 |
申请号 |
US20060607743 |
申请日期 |
2006.12.01 |
申请人 |
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
LEE DAE WOO;YANG YIL SUK;KIM GYU HYUN;YEO SOON IL;KIM JONG DAE |
分类号 |
H03K3/289 |
主分类号 |
H03K3/289 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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