| 摘要 |
A buck-boost converter is provided. In buck-boost mode, the converter operates in at least three phases. In one phase, the inductor current ramps upward. In another phase, the inductor current ramps downward. In yet another phase, the inductor current remains at roughly the same non-zero value. Only one pulse-width modulating signal is used in the buck-boost operation. A PWM comparator compares the pulse-width modulating signal with the error signal and trips when the error signal exceeds the pulse-width modulating signal. One of the three phases occurs at the beginning of the clock pulse before the PWM comparator trips. Another of the phases occurs while the PWM comparator is tripped. Yet another of the phases occurs from the time that the PWM goes from tripped to untripped until the beginning of the next clock cycle.
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