发明名称 Cascaded domino four-to-two reducer circuit and method
摘要 A cascaded differential domino four-to-two reducer. In an embodiment, the four-to-two reducer is constructed of a first three-to-two reducer and a second three-to-two reducer directly connected to the first three-to-two reducer. In a further embodiment, the first and second three-to-two reducer both include a symmetric carry generate gate.
申请公布号 US7392277(B2) 申请公布日期 2008.06.24
申请号 US20010893868 申请日期 2001.06.29
申请人 INTEL CORPORATION 发明人 FLETCHER THOMAS D.
分类号 G06F7/50;G06F7/60 主分类号 G06F7/50
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