发明名称 |
P-channel power chip |
摘要 |
An integrated circuit device for delivering power to a load includes a P-MOS power transistor, an N-MOS bypass transistor and a gate driver circuit. The P-MOS power transistor is coupled between a supply voltage node and a power output node of the integrated circuit device, and the N-MOS bypass transistor is coupled between the power output node and a reference node of the integrated circuit device. The gate driver circuit responds to a pulse-width-modulated (PWM) control signal by outputting an active-low drive-enable signal to a gate terminal of the P-MOS power transistor and an active-high bypass-enable signal to a gate terminal of the N-MOS bypass transistor during respective, non-overlapping intervals.
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申请公布号 |
US7391200(B1) |
申请公布日期 |
2008.06.24 |
申请号 |
US20070670924 |
申请日期 |
2007.02.02 |
申请人 |
NETLOGIC MICROSYSTEMS, INC. |
发明人 |
KHANNA SANDEEP;SRINIVASAN VARADARAJAN |
分类号 |
G06F1/18;G05F1/613;H01L25/00;H01L29/78 |
主分类号 |
G06F1/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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