发明名称 Data retention cell and data retention method based on clock-gating and feedback mechanism
摘要 For retaining an output data signal of a data retention cell in a power-saving mode, a slave latch unit of the data retention cell is powered with a real power for preserving the output data signal. The output data signal is furnished backward to an input control circuit of the data retention cell. The data signal furnished to a master latch unit of the data retention cell is controlled to switch between an input data signal and the output data signal by the input control circuit in response to a retention signal. The switching of the data signal for refreshing the master latch unit is delayed by a delay unit of the input control circuit, which functions to make sure that the data-preserving process is properly operated on any transition from the power-saving mode to a power-active mode.
申请公布号 US7391250(B1) 申请公布日期 2008.06.24
申请号 US20070849296 申请日期 2007.09.02
申请人 UNITED MICROELECTRONICS CORP. 发明人 CHUANG FU-CHAI
分类号 H03K3/356 主分类号 H03K3/356
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