| 摘要 |
The present invention provides a display device which can suppress the increase of a chip size while reducing the number of transistors of a decoder circuit compared to the prior art. Assuming m (m being an integer of 2 or more) as a lower-order bit in accordance with n-bit display data, a drive part includes a gray-scale voltage generating circuit which generates M pieces of gray-scale voltages where the gray scale number with respect to the gray-scale voltages is discontinuous, a decoder circuit which selects two neighboring gray-scale voltages out of M pieces of gray-scale voltages based on data of upper-order (n-m) bits in accordance with n-bit display data, and an output amplifying circuit which generates gray-scale voltages between two gray-scale voltages from two gray-scale voltages selected by the decoder circuit based on the data of lower-order m bits in accordance with n-bit display data and outputs the gray-scale voltages to the video lines.
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