| 摘要 |
Provided is a digital duty cycle corrector capable of generating a clock signal with the rate of duty 50:50, by means of three or more duty cycle correction circuits assigning different weight values to first and second clock signals that are different in duty cycle each other in order to reduce a phase difference between the first and second clock signals, and one or more duty cycle correction circuits assigning the same weight value to the first and second clock signals in order to eliminate a phase difference between the first and second clock signals.
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