| 摘要 |
Structures and methods that can be used to reduce power consumption in programmable logic devices (PLDs). Varying delays on the input paths of a PLD lookup table (LUT) can cause the nodes within the LUT (including the LUT output signal) to change state several times each time the input signals change state. Therefore, a programmable logic block for a PLD is provided that registers the LUT input signals instead of, or in addition to, the LUT output signal. The delays on the input paths are equalized and "glitching" on the LUT nodes is greatly reduced or eliminated. Thus, power consumption is reduced. Methods are also provided of reducing power consumption in PLDs by replacing single-bit registers on LUT output signals with multi-bit registers on LUT input signals, or by including multi-bit input registers in addition to the single-bit output registers.
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