| 摘要 |
A structure for a fast-serial finite field multiplier is provided to require a shorter delay than a serial multiplier and realize a faster speed by using smaller hardware than a parallel multiplier. A multiplication unit(200) includes a first multiplier(202) multiplying one even element corresponding to an 'm' exponent by a coefficient of even terms of B in turn while multiplying one even element corresponding to an 'm' exponent by alpha^2, and a second multiplier(204) multiplying one odd element, which is multiplied by alpha, by the coefficient of odd terms of B in turn while multiplying one multiplied odd element by alpha^2. An output unit(300) outputs a double speed serial multiplication value by adding a result of the first and second multipliers. The output unit comprises an m-bit register(310) and an adder(320) including m XOR gates.
|
