| 摘要 |
A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of N<SUB>f </SUB>NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of N<SUB>max-VC </SUB>NFETs are scanned and perform the function of voltage clamps and the remaining (N<SUB>f</SUB>-N<SUB>max-VC</SUB>) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity N<SUB>max-VC </SUB>based upon testing of the manufactured integrated circuit.
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