OVERLAY VERNIER OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

摘要

An overlay vernier of a semiconductor device and a method for manufacturing the same are provided to improve the margin of an alignment process and to increase the yield of a semiconductor manufacturing process by using divided patterns configuring a mother vernier whose widths are progressively decreased from the center of the mother vernier to both sides thereof. A layer to be etched is formed on an upper of an overlay vernier region on a semiconductor substrate. A photoresist pattern(120) for defining a mother vernier is formed on an upper of the layer to be etched. The mother vernier is comprised of one or more rectangular patterns. An inner of the rectangular pattern is comprised of slit-type divided patterns(140) that are arranged in a direction in parallel with a longitudinal direction of the rectangular pattern. Widths and pitches of the slit-type divided patterns are progressively decreased from the center of the rectangular pattern to both sides thereof. The layer to be etched is patterned by using the photoresist pattern as a mask to form the mother vernier.