STRESS ENGINEERING FOR SRAM STABILITY

摘要

Stress engineering for stabilizing an SRAM(static random access memory) is provided to improve stability and writability by including an integrated circuit including at least one SRAM cell having a gamma ratio not less than 1.0. At least one SRAM cell includes at least one nFET(n-channel field effect transistor)(14A,14C) and at least one pFET(p-channel field effect transistor)(14B,14D). A continuous relaxed stressed liner(24) is positioned on the at least one nFET and the at least one pFET. The continuous relaxed stressed liner can be made of a compressed stress material. The compressed stress material can be a silicon nitride. The continuous relaxed stressed liner can include at least one of a Xe ion or a Ge ion.