发明名称 LATCH CIRCUIT AND DESERIALIZER CIRCUIT
摘要 A latch includes a precharging unit, a memory logic unit, an input amplifying unit, and a clock synchronization switch. The memory logic unit and the input amplifying unit are arranged in a same transistor level. Thus, the latch has three transistor levels. Further, a current supply 150 is connected to the memory logic unit to control a current flowing through the memory logic unit.
申请公布号 US2008144399(A1) 申请公布日期 2008.06.19
申请号 US20070942922 申请日期 2007.11.20
申请人 FUJITSU LIMITED 发明人 CHEUNG TSZSHING
分类号 G11C7/00 主分类号 G11C7/00
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