CASCADED RADIX ARCHITECTURE FOR HIGH-SPEED VITERBI DECODER

摘要

A Viterbi decoder includes a branch metric unit (25) for generating branch metrics between two states at two different time periods, a traceback unit (27), a traceback memory (28) and an add-compare-select circuit unit (26). The add-compare-select circuit includes a plurality of cascaded add-compare-select sub-circuits, each add-compare-select sub-circuit calculating a path metric responsive to a plurality of branch metrics from the branch metric unit and a plurality of pre-calculated path metrics, where at least one of the add-compare-select sub-circuits receives a set of pre-calculated path metrics from another one of the add-compare-select sub-circuits.