发明名称 SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor device for preventing erroneous operations by suppressing a current flowing into peripheral circuits of a power transistor, while increase in a chip area is not permitted. SOLUTION: The semiconductor device is constituted to include a P-type semiconductor substrate 1, a P-type well layer 2 selectively formed on the P-type semiconductor substrate 1, a N<SP>+</SP>-type source layer 5 selectively formed on the P-type well layer 2, a N<SP>+</SP>-type drain layer 6 (N-type field moderating layer 7) formed on the P-type well layer 2 and separated from the N<SP>+</SP>-type source layer 5, a gate electrode 17 formed between the N<SP>+</SP>-type source layer 5 and the N<SP>+</SP>-type drain layer 6 via an insulating layer 16, a first trench 4 formed by surrounding the P-type well layer 2, namely by digging down the P-type semiconductor substrate 1 between the P-type well layer 2 and the N-type well layer 3, and a N<SP>+</SP>-type diffusing layer 12 formed within the first trench 4, in order to set the P-type source layer 5 and the N-type diffusing layer 12 in the equal electrical potential. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008140824(A) 申请公布日期 2008.06.19
申请号 JP20060323136 申请日期 2006.11.30
申请人 TOSHIBA CORP 发明人 NAKAMURA KAZUTOSHI
分类号 H01L27/08;H01L21/822;H01L27/04;H02M3/155 主分类号 H01L27/08
代理机构 代理人
主权项
地址