发明名称 BUS BRIDGE DEVICE, INFORMATION PROCESSOR, AND DATA TRANSFER CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To improve memory access efficiency while maintaining data coherency. SOLUTION: A register 134 stores an upper limit address and a predetermined lower limit address. An address comparison part 135 compares an address designated by an access request with the upper limit address and lower limit address stored in the register 134. When the designated address is within the range of the lower limit address and the upper limit address, the address comparison part 135 validates a first path for accessing a shared memory 200 through a cache 121. When the designated address is below the lower limit address or beyond the upper limit address, the address comparison part 135 validates a second path for accessing the shared memory 200 without through the cache 121. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008140078(A) 申请公布日期 2008.06.19
申请号 JP20060325020 申请日期 2006.11.30
申请人 TOSHIBA CORP 发明人 SATO MAKOTO
分类号 G06F12/08;G06F13/36 主分类号 G06F12/08
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