| 摘要 |
<p>An interface receive circuit, in which a frequency bandwidth is not limited, a jitter which may occur in an output signal is minimized, and a range of a common mode voltage of a differential input signal is not limited, is provided. The interface receive circuit includes a dual gate input stage, a first output stage, and a second output stage. The dual gate input stage generates first and second node voltages in response to differential input signals. The first output stage operates in response to the second bias voltage, stabilizes the first and second node voltages and VB by using a negative feedback stabilizer, and outputs third and fourth node voltages. A second output stage generates an output signal by using the third and fourth node voltages.</p> |
