| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of reducing wiring for control when a plurality of semiconductor memories are used. <P>SOLUTION: An input buffer 11 receives a chip-enable signal from the outside and outputs signals CEIN to input buffers 13-m to 13-O, thus outputting addresses supplied to terminals A<m> to A<O> to a memory array via the buffers 13-m to 13-O, reading data from the memory array, and supplying the data to output buffers 17-n to 17-O. An input buffer 14 receives a chip selection address inputted to a terminal AD from the outside and compares it with an internal address, and outputs a chip selection signal CEIN2 when both agree. An input buffer 15 receives the chip selection signal CEIN2, and outputs an output instruction signal OEIN when receiving an output instruction from the outside. The output buffers 17-n to 17-O are enabled by receiving the output instruction signal OEIN and output data read from the memory array to data terminals D<n> to D<O>. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
