| 摘要 |
A delay time of a reference clock CLK is changed to generate a memory control clock CLKd, a data value output from a write data generating section is written in a memory based on the memory control clock CLKd, while successively changing the delay time of the memory control clock CLKd with respect to the reference clock CLK, the data value written in the memory is read, and the delay time suitable for access to the memory is selected from the delay time of the memory control clock CLKd with respect to the reference clock CLK based on a comparison result of the data values.
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