发明名称 DATA PROCESSOR
摘要 PROBLEM TO BE SOLVED: To debug a program by use of conventional debugging device and debugger while suppressing increase of hardware. SOLUTION: The data processor includes a main storage 110 storing a plurality of instruction streams and a processor 120 executing an instruction stream transferred from the main storage 110. The processor 120 comprises: an instruction RAM 121 storing the instruction stream transferred from the main storage 110; an allocation address setting part 122 setting an allocation address on a memory space of the instruction RAM 121 so that the allocation address on the memory space of the instruction stream stored in the instruction RAM 121 does not overlap with the allocation address on the instruction RAM 121 of another instruction stream; and an instruction fetch control part 123 determining an access object space of instruction fetch access, based on the allocation address set by the arrangement address setting part 122, and accessing one of the main storage 110 and the instruction RAM 121 according to the determination result. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008140124(A) 申请公布日期 2008.06.19
申请号 JP20060325565 申请日期 2006.12.01
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HIGUCHI KOUTARO;MIYAJI SHINYA
分类号 G06F11/28 主分类号 G06F11/28
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