发明名称 |
High performance raid-6 system architecture with pattern matching |
摘要 |
An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are provided to allow P and Q type syndromes to be computed on a stripe in a single-pass of the data through the acceleration unit.
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申请公布号 |
US2008148025(A1) |
申请公布日期 |
2008.06.19 |
申请号 |
US20060642315 |
申请日期 |
2006.12.19 |
申请人 |
GOPAL VINODH;WOLRICH GILBERT;YAP KIRK S;FEGHALI WAJDI K;VRANICH JOHN;OTTAVI ROBERT P |
发明人 |
GOPAL VINODH;WOLRICH GILBERT;YAP KIRK S.;FEGHALI WAJDI K.;VRANICH JOHN;OTTAVI ROBERT P. |
分类号 |
G06F7/44 |
主分类号 |
G06F7/44 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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