| 摘要 |
PROBLEM TO BE SOLVED: To overcome the problem in a conventional SRAM memory cell for low-voltage operation that a static noise margin, which is an operation margin for a memory cell, decreases when a threshold of an MOS transistor configuring the memory cell is lowered. SOLUTION: A configuration is adopted where a power supply voltage Vdd', which is higher than a power supply voltage Vdd of a peripheral circuit power line 2, is supplied to a memory cell array 30 from a memory cell power line 4 as a power supply voltage of the memory cell. A conductance of a drive MOS transistor increases, so that the threshold of the MOS transistor can be lowered without decreasing the static noise margin, and the ratio of a gate width between the drive MOS transistor and a transfer MOS transistor can be set 1. Consequently it is possible to reduce a memory cell area. COPYRIGHT: (C)2008,JPO&INPIT
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