| 摘要 |
<P>PROBLEM TO BE SOLVED: To lower wiring resistance and parasitic inductance while preventing cracking of a pad and a lower layer wiring as well as breakage of a semiconductor element, and shortening the effective length of wiring, with no addition of a manufacturing process. <P>SOLUTION: A top wiring combined with electrode layer 58 is arranged just above a cell part where an LDMOS10 which is to be a power element is formed. A top wiring layer that is electrically connected to the element in the cell part and the electrode layer constituting a part of the pad structure are shared by the top wiring combined with electrode layer 58. <P>COPYRIGHT: (C)2008,JPO&INPIT |
