发明名称 |
PHASE LOCKED LOOP WITH ADAPTIVE PHASE ERROR COMPENSATION |
摘要 |
An adaptive phase-locked loop (PLL) circuit produces an output signal having a frequency in reference to the frequency of a reference signal. The PLL circuit includes an oscillator configured to generate the output signal according to a frequency control signal, and a processing circuit configured to generate a feedback signal deriving from the output signal. An adjustable shift circuit is provided to time-shift the feedback signal. The PLL further includes a phase comparison circuit configured to generate a phase error signal indicating a phase error between the time-shifted feedback signal and the reference signal, and a control circuit configured to generate the frequency control signal based on the phase error signal. The adjustable shift circuit adjusts a time-shift amount to time-shift the feedback signal according to the phase error signal.
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申请公布号 |
US2008136532(A1) |
申请公布日期 |
2008.06.12 |
申请号 |
US20060608213 |
申请日期 |
2006.12.07 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
HUFFORD MICHAEL M.;NAVIASKY ERIC;CAVIGLIA TONY |
分类号 |
H03L7/089;H03L7/08;H03L7/085 |
主分类号 |
H03L7/089 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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