| 摘要 |
<P>PROBLEM TO BE SOLVED: To enhance the stability of a memory cell, while taking the dynamic stability of an SRAM into consideration. <P>SOLUTION: Capacitance elements (C1, C2) are connected with storage nodes (SN, /SN), by utilizing a process for fabricating the floating gate (FG) and the control gate (CG) of a flash memory cell. That is, the gate electrodes of the load transistors (PT1, PT2) and the driver transistors (NT1, NT2) of an SRAM are formed of interconnections of the same layer as that for the floating gate, and interconnections in the same wiring layer as those of the control gate are made to form a capacitor electrode, aligned with a load and the gate electrode of the driver transistor. <P>COPYRIGHT: (C)2008,JPO&INPIT |
