| 摘要 |
A phase locked loop with improved lock time is achieved using a controller coupled to receive a reference signal and operable to generate a frequency divider control signal based upon the reference signal to control operation of a frequency divider. The PLL further includes a phase frequency detector for producing an error signal indicative of a difference in phase or frequency between the reference signal and a feedback signal, a charge pump for generating a current pulse proportional to the error signal, a loop filter for filtering the current pulse to produce a control voltage and a voltage controlled oscillator for producing an oscillation based upon the control voltage. The frequency divider is coupled to receive the oscillation and is operable to divide the oscillation by a divide ratio to produce the feedback signal.
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