发明名称 Circuitry and method
摘要 A circuitry for differential amplifying, logical inversion, NAND and/or NOR operations is provided, which includes at least one depletion mode transistor having JFET characteristics. A method for determining the properties of an electrochemical circuitry is provided, including at least one semi-finished transistor, by applying a solidified electrolyte to selected sets of electrochemically active transistor elements is also provided.
申请公布号 US2008135883(A1) 申请公布日期 2008.06.12
申请号 US20070980359 申请日期 2007.10.31
申请人 ACREO AB 发明人 ARMGARTH MARTEN;CHEN MIAIOXIANG M.;NILSSON DAVID A.;BERGGREN ROLF M.;KUGLER THOMAS;REMONEN TOMMI M.;FORCHHEIMER ROBERT
分类号 H01L27/10;C09K9/02;G02F1/163;G11C13/02;H01L21/02;H01L21/316;H01L51/00;H01L51/30 主分类号 H01L27/10
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