| 摘要 |
A semiconductor integrated circuit is disclosed, which includes a plurality of memory circuits in which defective columns are relievable, mounted on one chip, each of the memory circuits having a multi-bit structure, a plurality of comparison circuit which are connected to output sides of the respective memory circuits, and compare multi-bit memory data items output from the associated memory circuits with multi-bit expected data, a logic circuit which consolidates multi-bit comparison results output from the comparison circuits, a replacement analysis circuit which is shared between the memory circuits, performs replacement analysis by processing multi-bit data output from the logic circuit, and generates relief information to relief the memory circuits, and a nonvolatile storage circuit which stores the relief information, and performs relief for the memory circuits by using the relief information.
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