| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock gating system generating no jitter in a supplied clock even when switching on/off of an enable signal for a clock gating. <P>SOLUTION: A logic gate circuit 2 for gating generating a gated clock supplied to a gating application circuit 100 and the logic gate circuit 3 for adjusting load having the same constitution as the logic gate circuit 2 for gating are connected in parallel at the output end of a clock buffer 1 supplying a clock to the gating application circuit 100 and a gating non-application circuit 200 for the clock. The enable signal E for the clock gating is input to the logic gate circuit 2 for gating, and an inverted enable signal EB that is obtained by polarity-inverting the enable signal E with an inverter 4 is input to the logic gate circuit 3 for adjusting load. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
