| 摘要 |
Integrated circuit apparatus and methods are described for inserting multi-V<SUB>dd </SUB>buffers within an interconnection tree during routing toward minimization of power under a delay constraint. Insertion of level converters is not necessary within the routing trees of the interconnect tree despite the insertion of the multi-V<SUB>dd </SUB>buffers. Techniques are described for controlling the dramatic complexity increment due to simultaneous delay and power consideration and increased buffer choices. Overhead reduction techniques are taught including: sampling based techniques, prediction based pruning techniques (PSP) and (PMP), and escape grid reduction, each of which are directed to multi-V<SUB>dd </SUB>buffer insertion. The resultant integrated circuits are routed with substantial power reductions over conventional routing.
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