| 摘要 |
A word line selecting circuit of a semiconductor memory apparatus having at least two memory areas and a plurality of word lines formed across the two memory areas is provided. The circuit includes: a decoder configured to decode an input address and configured to decode a word line corresponding to the decoded input address from the plurality of word lines; and an address counter configured to count the decoded input address such that the word lines in the memory areas are alternately selected according to a refresh signal.
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