发明名称 Unified Model for process variations in integrated circuits
摘要 A method of developing a statistical model for integrated circuits includes providing a set of test patterns; collecting a set of intra-die data from the set of test patterns; collecting a set of inter-die data from the set of test patterns; generating a total variation sigma (sigma_total) from the set of intra-die data and the set of inter-die data; appointing one of a global variation sigma (sigma_global) and a local variation sigma (sigma_local) as a first sigma, and a remaining one as a second sigma; generating the first sigma from one of the set of intra-data and the set of inter-data; generating the second sigma by removing the first sigma from the sigma_total; generating a corner model for global variations based on sigma_global and the set of inter-die data; and generating a corner model for local variations based on sigma_local and the set of intra-die data.
申请公布号 US2008140363(A1) 申请公布日期 2008.06.12
申请号 US20060638303 申请日期 2006.12.12
申请人 LIN CHUNG-KAI;HSIAO CHENG;LIU SALLY 发明人 LIN CHUNG-KAI;HSIAO CHENG;LIU SALLY
分类号 G06F17/18;G06F17/50 主分类号 G06F17/18
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