| 摘要 |
Disclosed is a method including a step for selecting a component, a step for preparing a timing database including terminal information, input/output attribute and AC specifications of the component selected, a step for creating a circuit diagram from circuit design information, a step for extracting connection information and performing timing verification, when component connection has been determined, a step for performing layout design including the placement and routing of the components, a step for extracting wiring lengths of a data line and a clock line for the components from a net list and the layout information to derive the wiring delay time of the data and clock lines, a step for checking, from the wiring delay time derived, whether or not a timing constraint for the component is met.
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