| 发明名称 |
METHOD AND APPARATUS FOR COORDINATING MEMORY OPERATION AMONG DIVERSELY-LOCATED MEMORY COMPONENTS |
| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a method and an apparatus for coordinating memory operation among diversely-located memory components. <P>SOLUTION: Wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to address bus propagation delay and data bus propagation delay. A timing signal for duplicating propagation delay of signals associated with an address signal and/or a control signal is used to coordinate of the memory operations. <P>COPYRIGHT: (C)2008,JPO&INPIT |
| 申请公布号 |
JP2008135063(A) |
申请公布日期 |
2008.06.12 |
| 申请号 |
JP20080027488 |
申请日期 |
2008.02.07 |
| 申请人 |
RAMBUS INC |
发明人 |
WARE FREDERICK A;TSERN ELY K;PEREGO RICHARD E;HAMPEL CRAIG E |
| 分类号 |
G06F12/00;G06F13/16;G06F13/40;G06F13/42;G11C8/00;G11C11/401;G11C29/00;G11C29/02 |
主分类号 |
G06F12/00 |
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