| 摘要 |
In implementing an encryption algorithm or the like in a computer, it is difficult to align timing at which an instruction is executed regardless of presence or absence of branch in a case of including a conditional branch instruction. In order to solve the problem, provided is an information processor ( 1 ), including: an instruction fetch unit (instruction fetch circuit 200 ) that fetches an instruction code to be executed to output the fetched instruction code; and an instruction decode unit (instruction decode circuit 300 ) that decodes the instruction code that is output from the instruction fetch unit, in which the instruction decode unit outputs, upon detection of the instruction code being a conditional branch instruction, a control signal to the instruction fetch unit so that fetch timing of the successive instruction code becomes identical with each other regardless of the presence or absence of the branch due to the branch condition.
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