| 摘要 |
A control circuit U1 comprises four PMOS transistors MP1 through MP4 and receives a voltage Vn and a voltage Vss. The transistors MP1 and MP3, and the transistors MP2 and MP4, are respectively connected in series between a reference power supply Vdd and a fixed voltage Vss. The gate terminal of the transistor MP2 is connected to the fixed voltage Vss. The reference current and replica current of a current mirror F1 respectively flow through NMOS transistors M1 and M2, of which the respective source terminals are connected to the Vss. The gate width of the transistor M2 is a quarter of that of the transistor M1. The drain terminal is connected to the gate terminals of the transistors MP1 and MP2. The connection point between the source terminal of the transistor MP2 and the drain terminal of the transistor MP3 is connected to the gate terminal of the transistor MP1, and the connection point between the source terminal of the transistor MP2 and the drain terminal of the transistor MP4 is connected to the gate terminal of the transistor MP2. The control circuit U1 controls the voltage at the gate terminal of the transistor M1 so as to make the overdrive voltage of the transistor M1 be Vn.
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