| 摘要 |
A semiconductor memory device is provided to reduce chip size, by arranging a plurality of second pads along a plurality of first pads, and arranging a first transistor, a second transistor, a third transistor and a fourth transistor around a first pad and a second pad. A memory array part(21) is arranged on a rectangular substrate(20), and comprises a plurality of memory cells accommodating data. A plurality of first pads are arranged along one side of the circumference of the substrate. A plurality of second pads are arranged in the inside, along the plurality of first pads. A plurality of first output transistors are arranged around the plurality of first pads, and output read-out data in the memory array part to the plurality of first pads. A plurality of second output transistors are arranged around the plurality of second pads, and output read-out data in the memory array part to the plurality of second pads. The first output transistor comprises a first complementary transistor having a first transistor and a second transistor, and the second output transistor comprises a second complementary transistor having a third transistor and a fourth transistor. |
