| 摘要 |
A device for fetching a program in a parallel processing support processor is provided to enable a predetermined algorithm to use a parallel processing architecture while reducing a chip size by using a parallel processing mode or a usual SIMD(Single Instruction stream, Multi Data streams) processor mode. A plurality of program memory banks(31) stores instructions. A fetcher(30) fetches one or a plurality of instructions stored in the program memory banks to an instruction decoder depending on an operation mode. The fetcher includes a selector(32-2) selectively outputting the instruction inputted from each program memory bank, and a program fetch controller(32-1) outputting address and bank control signals for each program memory bank depending on the operation mode, and controlling the selector. The instructions output to the instruction decoder form an instruction set to be processed in parallel.
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