SIMD PARALLEL PROCESSOR WITH SIMD/SISD/ROW/COLUMN OPERTAION MODES

摘要

An SIMD(Single Instruction Multiple Data) parallel processor capable of performing an SIMD, an SISD(Single Instruction Single Data), a row and a column operation is provided to adapt efficiently instruction level parallelism by performing the SIMD, the SISD, the row and the column operation respectively according to an application field, and to have better usability, efficiency and flexibility. An SIMD parallel processor includes plural processing units connected to one another. Each processing unit includes an instruction register, an instruction decoder, a register file selection circuit, a function unit and an LSU(Load Store Unit). The instruction register stores instructions inputted via an instruction bus. The instruction decoder decodes the instructions stored by the instruction decoder, and generates a control signal for selecting one among the SIMD, the SISD, the row and the column operation in correspondence with the decoded instructions. The register file selection circuit enables a register file to be matched with the control signal and is operated for transferring data of the enabled register file to an internal output bus of the enabled register file. The function unit processes the data transferred via the internal output bus in response to the control signal. The LSU controls data IO with an external device connected to a data bus and the register file in response to the control signal.