In one embodiment, a memory array is provided comprising one or more columns each comprising a plurality of bit cells divided into groups of bit cells with each group of bit cells controllably coupled to a separate bit line.
申请公布号
US7385865(B2)
申请公布日期
2008.06.10
申请号
US20040001870
申请日期
2004.12.01
申请人
INTEL CORPORATION
发明人
KHELLAH MUHAMMAD M.;SOMASEKHAR DINESH;YE YIBIN;PANDYA GUNJAN H.;DE VIVEK K.
