发明名称 |
Shallow trench isolation method for shielding trapped charge in a semiconductor device |
摘要 |
A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D<SUB>1 </SUB>and is above the second plane by a second distance D<SUB>2 </SUB>that is less than D<SUB>1</SUB>.
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申请公布号 |
US7385275(B2) |
申请公布日期 |
2008.06.10 |
申请号 |
US20060276132 |
申请日期 |
2006.02.15 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CANNON ETHAN HARRISON;CHANG SHUNHUA THOMAS;FURUKAWA TOSHIHARU;HORAK DAVID VACLAV;KOBURGER, III CHARLES WILLIAM |
分类号 |
H01L29/00;H01L21/762;H01L21/763 |
主分类号 |
H01L29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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