发明名称 |
Gate array integrated circuit including a unit cell basic layer having gate terminal regions allowing two contact pads to be disposed laterally |
摘要 |
A gate array integrated circuit forming part of a semiconductor integrated circuit includes a basic layer of a unit cell in which a PMOS and an NMOS transistor are connected with a poly-silicon strip. The poly-silicon strip has gate terminal regions formed to laterally extend to allow two or more contact pads or through-holes to be disposed in each gate terminal region. It is thus possible to improve wiring efficiency and also micro-miniaturization and yield of the gate array integrated circuit. A layout method for a gate array integrated circuit is also provided.
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申请公布号 |
US7385233(B2) |
申请公布日期 |
2008.06.10 |
申请号 |
US20050220657 |
申请日期 |
2005.09.08 |
申请人 |
OKI ELECTRIC INDUSTRY CO., LTD. |
发明人 |
UCHIDA HIROFUMI |
分类号 |
H01L27/10 |
主分类号 |
H01L27/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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