发明名称 |
Scalable shader architecture |
摘要 |
A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
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申请公布号 |
US7385607(B2) |
申请公布日期 |
2008.06.10 |
申请号 |
US20040938042 |
申请日期 |
2004.09.10 |
申请人 |
NVIDIA CORPORATION |
发明人 |
BASTOS RUI M.;ABDALLA KARIM M.;ROUET CHRISTIAN;TOKSVIG MICHAEL J. M.;RHOADES JOHNNY S.;ALLEN ROGER L.;TYNEFIELD, JR. JOHN DOUGLAS;KILGARIFF EMMETT M.;TAROLLI GARY M.;CABRAL BRIAN;WITTENBRINK CRAIG MICHAEL;TREICHLER SEAN J. |
分类号 |
G06F15/16;G06F15/80;G06T1/20;G06T15/00 |
主分类号 |
G06F15/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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