| 摘要 |
A cache architecture ( 16 ) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory ( 20 ). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register ( 32 ) defines a starting address for the contiguous block of main memory ( 20 ). The data array ( 38 ) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array ( 38 ) when the starting address is loaded into the register ( 32 ). As addresses are received from the processing core, hit/miss logic ( 46 ) the starting address register ( 32 ), a global valid bit ( 34 ), line valid bits ( 37 ) and control bits ( 24, 26 ) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory ( 20 ). The hit/miss logic ( 46 ) also determines whether a line should be loaded into the RAM set data array ( 38 ) or in the associated cache.
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