CML DELAY CELL WITH LINEAR RAIL-TO-RAIL TUNING RANGE AND CONSTANT OUTPUT SWING

摘要

A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a current source I₀, and a compensation circuit having switching point optimized inverters having a first plurality of transistors having a transconductance beta_pN and a second plurality of transistors having a transconductance beta_nN, wherein respective ratios of beta_nN/beta_pN determine an inverter switching point of respective switching point optimized inverters, the first and second plurality of transistors having gates coupled to the tuning voltage input of the CML delay cell, wherein the switching point optimized inverters are followed by weighted tail current sources M_0N that supply additional currents to the current source I₀ at a drain node of the third transistor.