发明名称 |
Memory cells with improved program/erase windows |
摘要 |
A semiconductor structure includes a memory cell in a first region and a logic MOS device in a second region of a semiconductor substrate. The memory cell includes a first gate electrode over the semiconductor substrate; a first gate spacer on a sidewall of the first gate electrode, wherein the first gate spacer comprises a storage on a tunneling layer; and a first lightly-doped source or drain (LDD) region and a first pocket region adjacent to the first gate electrode. The logic MOS device includes a second gate electrode on the semiconductor substrate; a second gate spacer on a sidewall of the second gate electrode; a second LDD region and a second pocket region adjacent the second gate electrode, wherein at least one of the first LDD region and the first pocket region has a higher impurity concentration than a impurity concentration of the respective second LDD region and the second pocket region.
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申请公布号 |
US2008128791(A1) |
申请公布日期 |
2008.06.05 |
申请号 |
US20060633719 |
申请日期 |
2006.12.05 |
申请人 |
LEE TZYH-CHEANG;YANG FU-LIANG |
发明人 |
LEE TZYH-CHEANG;YANG FU-LIANG |
分类号 |
H01L27/115;H01L21/8246 |
主分类号 |
H01L27/115 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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