摘要 |
Embodiments of the invention relate to RF receiver technology and are particularly concerned with aspects of decoding data received at low data rates. In one arrangement, an RF receiver comprises a signal processor arranged to perform a method of decoding data contained within a signal that comprises a set of slots, at least one said slot comprising a preamble portion and a payload portion and being transmitted at a predetermined transmission frequency. The signal processor is arranged to perform a first process to derive timing data from the preamble portion and perform a second process to extract information from the payload portion, the second process being triggered from said timing data derived from the first process. The preamble portion comprises at least a first sequence of data and a second sequence of data, and the second sequence is the inverse of the first sequence. In preferred embodiments the first process comprises identifying a transition between said first and second sequences of data and deriving said timing data from the identified transition. The sequences of data can be embodied as a repeating pattern comprising at least two elements, e.g. first sequence can comprise 24 pairs of {1, 0} "dotting" and the second sequence can comprise 8 pairs of {0, 1} "anti- dotting". This transposition, or interface, between the first and second sequences is identified by components of the signal processor, and enables the receiver to identify bit timing associated with the preamble. |
申请人 |
PLEXTEK LIMITED;MASSAM, PETER, DAVID;BOWDEN, PHILIP, ALAN;HOWE, TIMOTHY, DAVID;JACKSON, TIMOTHY |
发明人 |
MASSAM, PETER, DAVID;BOWDEN, PHILIP, ALAN;HOWE, TIMOTHY, DAVID;JACKSON, TIMOTHY |