| 摘要 |
<p>A phase change memory device and a method for manufacturing the same are provided to lower an operation voltage of the phase change memory device by forming a buried common source line in a trench of a semiconductor substrate. An isolation layer(201) is formed in a surface of a semiconductor substrate(200). A trench is formed on a common source formation region of a semiconductor substrate. A buried common source line(203) is formed in the trench. A gate(204) is arranged on the substrate and formed between the buried common source lines. A drain(202b) is formed so that a transistor is formed in the substrate surface at a side of the gate on which the buried common source line is not formed. A first interlayer dielectric(291) is formed on the substrate to cover the transistor. A lower electrode(207) includes a contact plug(206) which is configured to contact to the drain in the first interlayer dielectric. A second interlayer dielectric(292) is formed on the first interlayer dielectric to cover the lower electrode. A lower electrode contact(208) is contacted to the lower electrode in the second interlayer dielectric. A phase change layer(209) and an upper electrode(210) are laminated on the lower electrode contact. A third interlayer dielectric(293) is formed on the second interlayer dielectric to cover the upper electrode and the phase change layer. An upper electrode contact(211) is formed to be contacted to the upper electrode in the third interlayer dielectric. A bit line(212) is formed on the third interlayer dielectric including the upper electrode contact.</p> |
